Evaluation of the characteristics of open BCH and RS code decoders implemented on modern FPGAs

The performance of existing data transmission and storage systems depends significantly on the hardware error control and correction units they employ. One effective method for combating errors is error-correcting coding, which allows for the correction of errors that occur during the transmission or storage of information. Developing hardware error-correcting coding units to meet specific requirements is a complex task. The competitiveness of the final product depends significantly on the quality of the solution to this problem. This paper describes a section of the library of error-correcting decoders dedicated to one of the most interesting classes of block linear codes – Bose-Chaudhuri-Hocquenghem codes (BCH codes) – and their most important subclass, non-binary BCH codes, Reed-Solomon codes (RS codes). A feature of the library is that the characteristics of all the blocks included in it were calculated using a single modern hardware base. Furthermore, the paper presents methods for comparing decoders implemented on different hardware platforms. The library of error-correcting decoders will help developers familiarize themselves with existing codecs early in the development process and potentially choose one over developing their own. The library will also help codec developers compare their codecs with existing ones. Furthermore, the library will be useful when developing new decoding algorithms designed for hardware implementation.

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